The neverending quest to eliminate all the design rules violations (in Altium)

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In theory the Design Rule Chcecker is a great tool, but in practice it´s always been like the fable about the boy who cried «wolf!» In case anyone reads this and isn´t familiar with the story: a young shepherd on top of the hill near his village gets bored and starts yelling «wolf!» to stir up some excitement, but after several false alarms the villagers stop paying attention. Then a real wolf shows up one day and when the boy sounds the alarm, no one comes.
And that´s how DRC has behaved for me for as long as I´ve used Altium. I started with Protel 98 at CPES, the lab at Virginia Tech, so that´s 16 years of false alarms, and in my last PCB design the metaphorical «wolf» finally showed up. An un-connected net was mixed in with the hundreds of other errors I´ve come to ignore over the years, and I missed it!
This put me on a quest to really dig into my design rules, mostly lifted from Altium defaults. But there´s one that I want some help with, «Minimum solder mask sliver constraint». Here´s a picture:Minimum solder mask sliver

The violation is that there´s an area between the soldermask around the via and the soldermask around the pad of the resistor that measures less than 0.254mm.

My main question: who cares?! I´m guessing that there´s some sort of manufacturing difficulty with small slivers of soldermask. But how small can they be before a PCB gets too be too expensive or too complicated to manufacture?

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